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LTC3209-1/LTC3209-2
OPERATIO
REGA, MAIN LED 8-Bit DAC Data
MSB
LSB
A7
MAIN D7
A6
MAIN D6
A5
MAIN D5
A4
MAIN D4
A3
MAIN D3
A2
MAIN D2
A1
MAIN D1
A0
MAIN D0
REGB, CAMERA LED 4-Bit High and 4-Bit Low DAC Data
MSB
HIGH BITS
LSB
MSB
LOW BITS
LSB
B7
CAM D3
B6
CAM D2
B5
CAM D1
B4
CAM D0
B3
CAM D3
B2
CAM D2
B1
CAM D1
B0
CAM D0
REGC, AUX Data and Option Byte
MSB
LSB
C7
Force2x
C6
Force1p5
C5
Dth2
C4
Dth1
C3
Scamhilo
C2
Drop2ms
C1
DAUX1
C0
DAUX0
DAUX0
DAUX1
AUX DAC Data (LSB)
AUX DAC Data (MSB)
Drop2ms
Scamhilo
Dth1
Dth2
Force1p5
Force2x
1
0
1
0
0
0
1
0
1
Changes Dropout Time from 150ms to 2ms
Dropout Time is 150ms Unless CAMHL is Enabled and High
Selects CAM High Register, Disables CAMHL Pin
Selects CAM Low Register, Enables CAMHL Pin
Must Always be 0 (Test Mode)
Must Always be 0 (Test Mode)
Forces Charge Pump into 1.5x Mode, CPO Regulates at 4.6V
Enables Mode Logic to Control Mode Changes Based on Dropout Signal
Forces Charge Pump into 2x Mode, Overrides Force1p5 Signal, CPO Regulates at 5.1V
0
I 2 C Interface
Enables Mode Logic to Control Mode Changes Based on Dropout Signal
Bus Speed
The LTC3209-1/LTC3209-2 communicates with a host
(master) using the standard I 2 C 2-wire interface. The
Timing Diagram (Figure 5) shows the timing relationship
of the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
The I 2 C port is designed to be operated at speeds of up to
400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I 2 C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
resistors or current sources, such as the LTC1694 SMBus
accelerator, are required on these lines.
The LTC3209-1/LTC3209-2 is a receive-only (slave)
device.
320912fa
14
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